The miniaturization of electronic components has made it increasingly common to integrate devices with diverse characteristics on a single integrated circuit (IC) giving rise to what is known as a system on chip (SOC) technology. The various types of devices located on a system on chip IC typically have different operating voltages thus requiring multiple gate oxide layers of different thickness to be formed. For example, a chip may have low, medium and high voltage device regions with the gate oxide associated with the field effect transistors (FET) in the high voltage region being the thickest and the gate oxide associated with the FETs in the low voltage device region being the thinnest. Chips having FETs formed as such are referred to as triple gate oxide (TGO) chips.
In order to form three different gate oxide thicknesses on the respective device regions of a TGO chip, several oxide removal and growth steps have to be carried out. However, the oxide removal processes have a detrimental impact on the shallow trench isolation (STI) structures which are commonly used as a means of isolation between adjacent FETs. For example, referring to FIG. 1 which depicts a portion of a TGO chip, a STI structure 2 is shown sandwiched between two active semiconductor regions 3 and 4. The STI structure 2 is made up of a trench 5 formed in a substrate and filled with trench oxide 6. The peripheral edges of the trench oxide 6 are recessed below the top surface of the trench oxide giving rise to what are known as divots 8. These divots 8 are formed at the edges of the STI during oxide removal as the trench oxide etch rate is higher at the peripheral edges.
The divots 8 in the STI structures 2 are undesirable as they increase the sub-threshold leakage current of transistors in the adjacent active semiconductor regions 3, 4. This effect is particularly significant for the low voltage regions with thin gate oxide transistors. Therefore, it is desirable to provide a method for fabricating a TGO chip in which divot formation in the STI structures is reduced.